1. The Field of the Invention
Embodiments of the present invention relate generally to programmable frequency clocks. More specifically, disclosed embodiments relate to programmable frequency clocks in optical transceivers that control the speed of high speed comparison in the optical transceiver.
2. The Relevant Technology
Computing and networking technology have transformed our world. As the amount of information communicated over networks has increased, high speed transmission has become ever more critical. Many high speed data transmission networks rely on optical transceivers and similar devices for facilitating transmission and reception of digital data embodied in the form of optical signals over optical fibers. Optical networks are thus found in a wide variety of high speed applications ranging from as modest as a small Local Area Network (LAN) to as grandiose as the backbone of the Internet.
The operation of an optical transceiver is susceptible to its operating environment and to other operational parameters. Changes in operational parameters such as temperature or laser bias current can have an effect on the output performance of the optical transceiver. To help monitor any operational parameter changes, the optical transceiver may include a comparator circuit.
A comparator circuit is used to make comparisons between actual operational parameter values and desired operational parameter values. For example, a comparator may take a measured operational temperature value and compare that with a desired operational temperature value. The result of the comparison may then be reported to other circuitry in the optical transceiver. If the comparison is outside of an acceptable range, then the optical transceiver may take appropriate action. Thus it can be seen that the speed of the comparator circuit is very important. The faster the comparator can produce a comparison result, the faster the optical transmission device can make any needed adjustments.
In many cases, the speed of the comparator circuit is driven by the speed of the clock signal that controls the rate at which signals representing the desired operational parameter values are received by the actual analog comparators within the high speed comparator circuit. These signals are usually digital and must be converted to analog by a Digital to Analog Converter (hereinafter also referred to as “DAC”) contained within the comparator circuit. However, the DAC can only efficiently operate at certain clock speeds. This is due to physical limitations in the silicon that the DAC has been implemented in. If the clock speed is too fast, the desired operational parameter values may arrive at the input to the DAC before the DAC is ready, causing potentially inaccurate comparisons. On the other hand, if the clock speed is too slow, time is wasted as the comparison process is slower than necessary.
One solution to this problem is to measure the actual silicon speed of each DAC and determine the clock speed accordingly. This is time consuming and problematic if multiple DACs are from different silicon wafers. Another approach is to find a range of speeds that the different DACs can efficiently operate at and set the clock speed accordingly. For example, if the DACs can efficiently operate at a clock cycle period ranging from 93 nanoseconds (ns) to 370 ns, then the clock period would need to be approximately 400 ns to ensure each DAC can efficiently operate at the clock speed under the worst case scenario. Accordingly, the clock period could be set at 400 ns even if the actual DAC is able to efficiently operate at clock periods as short as 93 ns. Again, valuable time is wasted as the clock speed is not as fast as it could be.
Therefore, what would be advantageous is for a mechanism that allows for more optimal high speed comparisons regardless of the particular silicon instantiation of the DAC.